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| (R) UCT MENT ROD E TE P EPLAC nter at LE BSO NDED R port Ce m/tsc O o up ME rsil.c cal S COM REData echni ww.inte NO t our T Sheet w IL or ac cont -INTERS 8 1-88 EL5287 January 18, 2002 FN7191 Window 4ns High-Speed Comparator The EL5287 comparator is designed for operation in single supply and dual supply applications with 5V to 12V between VS+ and VS-. For single supplies, the inputs can operate from 0.1V below ground for use in ground sensing applications. The output side of the comparators can be supplied from a single supply of 2.7V to 5V. The rail-to-rail output swing enables direct connection of the comparator to both CMOS and TTL logic circuits. The latch input of the EL5287 can be used to hold the comparator output value by applying a low logic level to the pin. The EL5287 is a window comparator. A single input is compared with a high reference and a low. When the output goes beyond one of these reference signals, the relevant output goes low. The EL5287 is available in the 10-pin MSOP package and is specified for operation over the full -40C to +85C temperature range. Also available are a single (EL5185) and quad versions (EL5485 and EL5486). Features * 4ns typ. propagation delay * 5V to 12V input supply * +2.7V to +5V output supply * True-to-ground input * Rail-to-rail outputs * Separate analog and digital supplies * Active low latch * Single available (EL5185) * Dual available (EL5285) * Quad available (EL5485 & EL5486) * Pin-compatible 6ns family available (EL5x81, EL5283 & EL5482) Applications * Threshold detection * High speed sampling circuits * High speed triggers * Line receivers Pinout EL5287 (10-PIN MSOP) TOP VIEW * PWM circuits * High speed V/F converters VS+ 1 VREFH 2 IN 3 VREFL 4 VS- 5 + + - 10 VSD 9 OUTH 8 LATCH 7 OUTL 6 GND Ordering Information PART NUMBER EL5287CY EL5287CY-T13 PACKAGE 10-Pin MSOP 10-Pin MSOP TAPE & REEL 13" PKG. NO. MDP0043 MDP0043 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners. EL5287 Absolute Maximum Ratings (TA = 25C) Analog Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . +12.6V Digital Supply Voltage (VSD to GND). . . . . . . . . . . . . . . . . . . . . .+7V Differential Input Voltage . . . . . . . . . . .[(VS-) -0.2V] to [(VS+) +0.2V] Common-mode Input Voltage . . . . . . .[(VS-) -0.2V] to [(VS+) +0.2V] Latch Input Voltage . . . . . . . . . . . . . . . . . . . . -0.2V to [(VSD) +0.2V] Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 125C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER INPUT VOS IB CIN IOS VCM CMRR OUTPUT VOH VOL VS = 5V, VSD = 5V, RL = 2.3k, TA = 25C, unless otherwise specified. CONDITION MIN TYP MAX UNIT DESCRIPTION Input Offset Voltage Input Bias Current Input Capacitance Input Offset Current Input Voltage Range Common-mode Rejection Ratio VCM = 0V, VO = 2.5V -10 1 -5 5 4 mV A pF VCM = 0V, VO = 2.5V -2.5 (VS-) - 0.1 0.5 2.5 (VS+) - 2.25 A V dB -5.1V < VCM < +2.75V 65 90 Output High Voltage Output Low Voltage VIN > 250mV VIN > 250mV VSD - 0.6 VSD - 0.4 GND + 0.25 GND + 0.5 V V DYNAMIC PERFORMANCE tpd+ tpdSUPPLY IS+ ISISD Positive Analog Supply Current Per comparator 12 7.5 5.5 0.9 55 80 13.5 8.5 6.5 1.2 mA mA mA mA dB Positive Going Delay Time Negative Going Delay Time VIN = 1VP-P, VOD = 50mV VIN = 1VP-P, VOD = 50mV 4 4 6 6 ns ns Negative Analog Supply Current Per comparator Digital Supply Current at No Load Power Supply Rejection Ratio Per comparator, output high Per comparator, output low PSRR LATCH VLH VLL ILH ILL td + td ts th tpw(D) Latch Input Voltage High Latch Input Voltage Low Latch Input Current High Latch Input Current Low Latch Disable to High Delay Latch Disable to Low Delay Minimum Setup Time Minimum Hold Time Minimum Latch Disable Pulse Width VLH = 3.0V VLL = 0.3V 0.8 -50 -50 -30 -40 4 4 2 1 5 2.0 V V A A ns ns ns ns ns 2 EL5287 Typical Performance Curves Supply Current vs Supply Voltage 14 12 10 IS (mA) 8 6 4 4.2 2 0 0 1 2 3 VS (V) Offset Voltage vs Temperature 2.5 2 1.5 VOS (mV) 1 0.5 0 -0.5 -50 IB (A) 9 8 7 6 5 4 3 2 -30 -10 10 30 50 70 90 4 5 6 ISVIN=-50mV RL=2.3k 4.8 IS+ VOH (V) 4.6 5 Output High Voltage vs Temperature 4.4 4 -50 -30 -10 10 30 50 70 90 Temperature (C) Input Bias Current vs Temperature 1 -50 -30 -10 10 30 50 70 90 Temperature (C) Output Low Voltage vs Temperature 0.4 14 12 Supply Current (mA) Temperature (C) Supply Current vs Temperature (per comparator) IS+ 10 8 6 4 2 IS- 0.3 VOL (V) 0.2 0.1 -50 -30 -10 10 30 50 70 90 0 -50 -30 -10 10 30 50 70 90 Temperature (C) Temperature (C) 3 EL5287 Typical Performance Curves (Continued) 4.2 4.1 Delay Time (ns) 4 3.9 3.8 3.7 3.6 Propagation Delay vs Overdrive VIN=1VSTEP VS=5V VSD=5V RL=2.3k TPD+ Delay Time (ns) Propagation Delay vs Supply Voltage 4.5 4.4 4.3 4.2 4.1 4 3.9 3.8 3.7 3.6 3.5 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6 VS (V) Digital Supply Current vs Switching Frequency (per comparator) 25 VS=5V VSD=5V RL=2.3k VS=5V TA=25C RL=2.3k TPDTPD+ VSD=VS+ VOD=50mV RL=2.2k TPD- 3.5 50 100 150 200 250 300 350 400 450 500 550 600 VOD (mV) Propagation Delay vs Overdrive VIN=3VSTEP 6.8 6.6 6.4 Delay Time (ns) 6.2 6 5.8 5.6 5.4 5.2 20 TPD+ ISD (mA) 15 VSD=5V VSD=3V TPD- 10 5 5 0.2 0 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 10 20 30 40 50 VOD (V) Frequency (MHz) Propagation Delay vs Source Resistance VIN=1VSTEP VS=5V VSD=5mV VOD=50mV RL=2.3k TPD+ TPD- 7.2 7 Delay Time (ns) 6.8 6.6 6.4 6.2 6 Propagation Delay vs Overdrive VIN=5VSTEP VS=5V VSD=5V RL=2.3k Delay Time (ns) 16 14 12 10 8 6 4 TPD+ TPD- 5.8 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOD (V) 2 2.2 2.4 2.6 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Source Resistance (k) 4 EL5287 Typical Performance Curves (Continued) 7.5 7 Delay Time (ns) 6.5 6 5.5 5 4.5 4 Propagation Delay vs Load Capacitance VIN=1VSTEP VS=5V VSD=5V VOD=50mV RL=2.3k TPD+ TPD- Package Power Dissipation vs Ambient Temp. JEDEC JESD51-3 Low Effective Thermal Conductivity Test Board 0.6 0.5 Power Dissipation (W) 0.4 0.3 0.2 0.1 0 486mW M SO P1 20 0 6 C/ W 0 10 20 30 40 50 60 70 80 90 100 0 25 CLOAD (pF) Package Power Dissipation vs Ambient Temperature JEDEC JESD51-7 High Effective Thermal Conductivity Test Board 1 870mW M S 11 OP1 5 0 C/ W 50 75 85 100 Ambient Temperature (C) 125 Output with 50MHz Input VIN=1VP-P Power Dissipation (W) 0.8 0.6 0.4 Output (5ns/div, 2V/div) Input (5ns/div, 0.5V/div) 0.2 0 0 25 50 75 85 100 125 Ambient Temperature (C) Output with 50MHz Input VIN=3VP-P Output (5ns/div, 2V/div) Input (5ns/div, 2V/div) 5 EL5287 Timing Diagram Compare Latch Enable Input Latch Differenti al Input Voltage ts VIN th Latch Compare 1.4V Latch tpw(D) VOS VOD tpdtd+ Comparator Output 2.4V Definition of Terms TERM VOS VIN VOD tpd+ tpdtd + tdts th tpw (D) DEFINITION Input Offset Voltage - Voltage applied between the two input terminals to obtain CMOS logic threshold at the output Input Voltage Pulse Amplitude - Usually set to 1V for comparator specifications Input Voltage Overdrive - Usually set to 50mV and in opposite polarity to VIN for comparator specifications Input to Output High Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS logic threshold of an output low to high transition Input to Output Low Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS logic threshold of an output high to low transition Latch Disable to Output High Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high transition to the point of the output crossing CMOS threshold in a low to high transition Latch Disable to Output Low Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high transition to the point of the output crossing CMOS threshold in a high to low transition Minimum Setup Time - The minimum time before the negative transition of the latch signal that an input signal change must be present in order to be acquired and held at the outputs Minimum Hold Time - The minimum time after the negative transition of the latch signal that an input signal must remain unchanged in order to be acquired and held at the output Minimum Latch Disable Pulse Width - The minimum time that the latch signal must remain high in order to acquire and hold an input signal change 6 EL5287 Pin Descriptions PIN NUMBER 1 2 PIN NAME VS+ VREFH FUNCTION Positive supply voltage Upper voltage reference VS+ EQUIVALENT CIRCUIT VREF IN VSCircuit 1 3 4 5 6 7 IN VREFL VSGND OUTL Input Lower voltage reference Negative supply voltage Digital ground Low output (Reference Circuit 1) (Reference Circuit 1) VSD VS+ OUT VSCircuit 2 8 LATCH Latch VS+ LATCH VSD VSD VSCircuit 3 9 10 OUTH VSD High output Digital supply voltage (Reference Circuit 2) Applications Information Power Supplies and Circuit Layout The EL5287 comparator operates with single and dual supply with 5V to 12V between VS+ and VS-. The output side of the comparator is supplied by a single supply from 2.7V to 5V. The rail to rail output swing enables direct connection of the comparator to both CMOS and TTL logic circuits. As with many high speed devices, the supplies must be well bypassed. Elantec recommends a 4.7F tantalum in parallel with a 0.1F ceramic. These should be placed as close as possible to the supply pins. Keep all leads short to reduce stray capacitance and lead inductance. This will also minimize unwanted parasitic feedback around the comparator. The device should be soldered directly to the PC board instead of using a socket. Use a PC board with a good, unbroken low inductance ground plane. Good ground plane construction techniques enhance stability of the comparators. Input Voltage Considerations The EL5287's input range is specified from 0.1V below VSto 2.25V below VS+. The criterion for the input limit is that the output still responds correctly to a small differential input signal. The differential input stage is a pair of PNP transistors, therefore, the input bias current flows out of the device. When either input signal falls below the negative input voltage limit, the parasitic PN junction formed by the substrate and the base of the PNP will turn on, resulting in a significant increase of input bias current. If one of the inputs goes above the positive input voltage limit, the output will still maintain the correct logic level as long as the other input stays within the input range. However, the propagation delay will increase. When both inputs are outside the input voltage range, the output becomes unpredictable. Large differential 7 EL5287 voltages greater than the supply voltage should be avoided to prevent damages to the input stage. where: VS is the analog supply voltage from VS+ to VSIS is the analog quiescent supply current per comparator VSD is the digital supply voltage from VSD to ground ISD is the digital supply current per comparator N is the number of comparators in the package ISD strongly depends on the input switching frequency. Please refer to the performance curve to choose the input driving frequency. Having obtained the power dissipation, the maximum junction temperature can be determined as follows: T JMAX = T MAX + JA x P DISS Input Slew Rate Most high speed comparators oscillate when the voltage of one of the inputs is close to or equal to the voltage on the other input due to noise or undesirable feedback. For clean output waveform, the input must meet certain minimum slew rate requirements. In some applications, it may be helpful to apply some positive feedback (hysteresis) between the output and the positive input. The hysteresis effectively causes one comparator's input voltage to move quickly past the other, thus taking the input out of the region where oscillation occurs. For the EL5287, the propagation delay increases when the input slew rate increases for low overdrive voltages. With high overdrive voltages, the propagation delay does not change much with the input slew rate. where: TMAX is the maximum ambient temperature JA is the thermal resistance of the package Latch Pin Dynamics The EL5287 contains a "transparent" latch for each channel. The latch pin is designed to be driven with either a TTL or CMOS output. When the latch is connected to a logic high level or left floating, the comparator is transparent and immediately responds to the changes at the input terminals. When the latch is switched to a logic low level, the comparator output remains latched to its value just before the latch's high-to-low transition. To guarantee data retention, the input signal must remain the same state at least 1ns (hold time) after the latch goes low and at least 2ns (setup time) before the latch goes low. When the latch goes high, the new data will appear at the output in approximately 4ns (latch propagation delay). Window Detector If VIN is in the range of VREFL < VIN < VREFH, both outputs go high and the input in range is high. If VIN is out of the range set by VREFH and VREFL, the input in range is low. VREFH + - OUTH Input In Range VIN + - VREFL OUTL Power Dissipation When switching at high speeds, the comparator's drive capability is limited by the rise in junction temperature caused by the internal power dissipation. For reliable operation, the junction temperature must be kept below TJMAX (125C). An approximate equation for the device power dissipation is as follows. Assume the power dissipation in the load is very small: P DISS = ( V S x I S + V SD x I SD ) x N All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8 |
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